The present invention relates to nonvolatile erasable programmable memories and more specifically, techniques for erasing, programming, or reading these types of memories.
Memory and storage is one of the key technology areas that is enabling the growth in the information age. With the rapid growth in the Internet, World Wide Web (WWW), wireless phones, personal digital assistant, digital cameras, digital camcorders, digital music players, computers, networks, and more, there is continually a need for better memory and storage technology. A particular type of memory is nonvolatile memory. A nonvolatile memory retains its memory or stored state even when power is removed. Some types of nonvolatile erasable programmable memories include Flash, EEPROM, EPROM, MRAM, FRAM, ferroelectric, and magnetic memories. Some nonvolatile storage products include CompactFlash (CF) cards, MultiMedia cards (MMC), Flash PC cards (e.g., ATA Flash cards), SmartMedia cards, and memory sticks.
A widely used type of semiconductor memory storage cell is the floating gate memory cell. Some types of floating gate memory cells include Flash, EEPROM, and EPROM. The memory cells are configured or programmed to a desired configured state. In particular, electric charge is placed on or removed from the floating gate of a Flash memory cell to put the memory into two or more stored states. One state is an erased state and there may be one or more programmed states. Alternatively, depending on the technology and terminology, there may be a programmed state and one or more erased states. A Flash memory cell can be used to represent at least two binary states, a 0 or a 1. A Flash memory cell can store more than two binary states, such as a 00, 01, 10, or 11; this cell can store multiple states and may be referred to as a multistate memory cell. The cell may have more than one programmed states. If one state is the erased state (00), the programmed states will be 01, 10, and 11, although the actual encoding of the states may vary.
Despite the success of nonvolatile memories, there also continues to be a need to improve the technology. It is desirable to improve the density, speed, durability, and reliability of these memories. It is also desirable to reduce power consumption.
As can be seen, there is a need for improving the operation of nonvolatile memories. Specifically, by allowing background operation of the nonvolatile memory cells, this will speed up operations and reduce power consumption.
The invention provides a technique of erasing, programming, or reading nonvolatile memory cells by dynamically applying an operating voltage to the gates of the memory cells, rather than a continuous voltage. This reduces the power consumed during an operation. Dynamic operation such as dynamic erase, dynamic program, dynamic read, also permits any operation, such as read, program, or erase, to occur while selected memory cells are activated. Dynamic operation improves the operational speed of an integrated circuit compared to a continuous operation. This technique may also be referred to as background operation, such as background erase, background program, or background read. In an embodiment, the gates are charged to an operational or operating voltage using a charge pump. The operational voltage may be an erase voltage, program voltage, or read voltage. The pump is then disconnected, and the gates remain at the voltage dynamically. The operating voltage at the gates will be periodically checked and refreshed as needed. While the charge pump is disconnected and the operating voltage is dynamically held at the gates, other operations, possibly on other memory cells, may be performed.
In one embodiment, the invention is a method of operating an integrated circuit with nonvolatile memory cells including turning on a charge pump to generate an erase voltage. One or more erase gates of nonvolatile memory cells selected for erase are charged with the erase voltage. The charge pump is disconnected. The charge pump may also be turned off after it is disconnected. The erase gates are allowed to hold the erase voltage dynamically while the charge pump is disconnected. The selected nonvolatile memory cells are erased using the dynamic erase voltage.
The charge pump may be periodically connected to refresh the erase voltage on the erase gates to refresh the erase voltage on the erase gates. Programming of nonvolatile memory cells, other than the nonvolatile memory cells selected for erase, is permitted while the charge pump is disconnected. Reading of nonvolatile memory cells, other than the nonvolatile memory cells selected for erase, is permitted while the charge pump is disconnected.
The selected nonvolatile memory cells may be checked to see whether they are erased. If the selected nonvolatile memory cells are not erased, the charge pump is connected to refresh the erase voltage on the erase gates. The operation may be repeated.
In another embodiment, the invention is a method of operating an integrated circuit including erasing, programming, or reading selected memory cells by dynamically charging gates of the selected memory cells by periodically directly applying an operational voltage to the gates. Operations on memory cells, other than the selected memory cells, are permitted when the operating voltage is not being directly applied to the gates. When the selected memory cells are considered erased, programmed, or read, the gates of the selected memory cells are discharged to ground. When the selected memory cells are erased, a VT of a floating gate transistor becomes uniformly positive or negative.
In another embodiment, the invention is an integrated circuit including an array of memory cells arranged in rows and columns. There are a number of transfer transistors, each connected to a row of the array of memory cells. There are a number of pumps, each connected to one of the transfer transistors. A pump dynamically charges gates of a row of memory cells to an operating voltage through a respective transfer transistor and the operating voltage is dynamically held at the gates by turning off the respective transfer transistor.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.